The field of edge computing is undergoing significant transformations, driven by the need for more flexible, secure, and efficient architectures. Recent research has focused on improving real-time scheduling, privacy, and scalability, with a growing emphasis on privacy-aware and decentralized inference orchestration.
One of the key areas of research is the development of novel operating system designs, such as modularized and demand-driven frameworks, to better manage heterogeneous platforms and limited resources. For instance, IslandRun introduces a multi-objective orchestration system for distributed AI inference, while TenonOS proposes a self-generating intelligent embedded operating system framework. Additionally, the Joint Partitioning and Placement of Foundation Models framework presents a runtime-resolved partitioning and placement of foundation models for real-time edge AI.
Another crucial aspect is the focus on security, efficiency, and portability in computing for resource-constrained devices. Researchers are exploring the use of WebAssembly (WASM) as a runtime environment for embedded IoT systems, which offers a good trade-off between performance and security. Noteworthy papers include the exploration of WebAssembly on resource-constrained IoT devices and the proposal of extended abstract synthesizable low-overhead circuit-level countermeasures.
The optimization of task allocation and resource management in complex networks is also a key direction in edge computing research. Innovative frameworks and algorithms are being developed to address computational, communication, and energy limitations in edge devices. The integration of multiple edge devices, such as unmanned aerial vehicles (UAVs) and low earth orbit (LEO) satellites, is providing efficient computing services. A paper proposing a binary integer linear programming-based formulation for task allocation in the edge/hub/cloud paradigm yields optimal and scalable results.
Lastly, edge AI is moving towards increased efficiency and scalability with the development of hardware-aware neural networks and novel number formats. Researchers are focusing on designing models and architectures that can optimize performance, power consumption, and area usage. The proposal of a variable-point number format for efficient multiplication of high-dynamic-range numbers and the development of hardware-aware neural architecture search frameworks for early exiting networks on edge accelerators are significant advancements.
Overall, these developments are pushing the boundaries of edge computing, enabling real-time and low-latency processing on resource-constrained devices, and making them suitable for deployment in various edge environments.
