The field of Electronic Design Automation (EDA) is witnessing significant advancements, driven by innovations in timing-driven global placement, setup/hold time characterization, and automatic test pattern generation. Researchers are exploring new techniques, such as critical path aware timing-driven global placement and bias-enhanced interpolation, to improve the performance and efficiency of EDA tools. Additionally, the use of machine learning and reinforcement learning is becoming increasingly popular in EDA, with applications in areas like detailed routing and analog circuit optimization. The development of new frameworks and tools, such as TD-Placer and SetupKit, is also contributing to the advancement of the field. Noteworthy papers include TD-Placer, which achieves an average 10% improvement in Worst Negative Slack and a 5% reduction in Critical Path Delay, and SetupKit, which demonstrates a significant 2.4x overall CPU time reduction in setup/hold time characterization. InF-ATPG is also notable for its intelligent FFR-driven ATPG framework, which reduces backtracks by 55.06% on average compared to traditional methods.
Advances in Electronic Design Automation
Sources
Critical Path Aware Timing-Driven Global Placement for Large-Scale Heterogeneous FPGAs
SetupKit: Efficient Multi-Corner Setup/Hold Time Characterization Using Bias-Enhanced Interpolation and Active Learning
InF-ATPG: Intelligent FFR-Driven ATPG with Advanced Circuit Representation Guided Reinforcement Learning
Exploiting Function-Family Structure in Analog Circuit Optimization
Drafting and Multi-Input Switching in Digital Dynamic Timing Simulation for Multi-Input Gates
Monomorphism-based CGRA Mapping via Space and Time Decoupling
SAT-MapIt: A SAT-based Modulo Scheduling Mapper for Coarse Grain Reconfigurable Architectures
Mapping code on Coarse Grained Reconfigurable Arrays using a SAT solver
Accelerating Detailed Routing Convergence through Offline Reinforcement Learning
FLEX: Leveraging FPGA-CPU Synergy for Mixed-Cell-Height Legalization Acceleration
Declarative Synthesis and Multi-Objective Optimization of Stripboard Circuit Layouts Using Answer Set Programming