The field of heterogeneous computing and hardware synthesis is moving towards more efficient and flexible design methodologies. Researchers are exploring new approaches to optimize performance, energy consumption, and productivity in heterogeneous systems. One notable trend is the development of novel hardware description languages and synthesis frameworks that can efficiently model and optimize complex designs. These advancements have the potential to significantly improve the performance and efficiency of various applications, including scientific workloads and network processing. Noteworthy papers in this area include: HeteroSTA, which introduces a CPU-GPU heterogeneous static timing analysis engine, and Cement2, which proposes temporal hardware transactions for high-level and efficient FPGA programming. Additionally, SkyEgg presents a joint implementation selection and scheduling framework for hardware synthesis using e-graphs, and EPSO introduces a caching-based efficient superoptimizer for BPF bytecode.