The field of neural network acceleration and optimization is moving towards the development of more efficient and scalable architectures. Recent research has focused on improving the performance and energy efficiency of neural network inference and training workloads. One notable trend is the integration of artificial and spiking neural networks to minimize energy-delay product and improve throughput. Another area of focus is the development of time-predictable hardware architectures that can provide high-performance and low-latency execution of neural networks. Additionally, researchers are exploring new execution frameworks and algorithms that can effectively utilize emerging architectures such as Arm SME. Noteworthy papers in this area include: NeuroFlex, which presents a column-level accelerator that co-executes artificial and spiking neural networks, achieving significant improvements in energy-delay product and throughput. MultiVic, which proposes a time-predictable RISC-V multi-core processor optimized for neural network inference, demonstrating low execution time fluctuation and high performance. LOOPS, which introduces a hybrid execution framework for sparse matrix-matrix multiplication on Arm SME architectures, achieving significant speedups and energy efficiency improvements.