The field of scientific computing and hardware design is witnessing significant advancements in compiler optimization and hardware design. Researchers are focusing on developing innovative methods to ensure the correctness of aggressive compiler optimizations, particularly in the context of floating-point optimizations. Additionally, there is a growing interest in high-level hardware design tools and methodologies to identify divergences in hardware designs for HPC workloads. The development of agile design frameworks for pairing-based cryptography and FPGA-accelerated hardware fuzzing for processor verification are also notable trends. Furthermore, system-technology co-optimization and automated kernel optimization using large language models are emerging as promising approaches to sustain scaling trends in the VLSI industry. Noteworthy papers include: Towards Verified Compilation of Floating-point Optimization, which presents a preliminary work on proving the correctness of FMA optimization. Finesse: An Agile Design Framework for Pairing-based Cryptography, which introduces a co-design methodology for PBC accelerators. TurboFuzz: FPGA Accelerated Hardware Fuzzing, which presents an end-to-end hardware-accelerated verification framework for modern processor verification. Orthrus: Dual-Loop Automated Framework for System-Technology Co-Optimization, which synergizes system-level and technology-level optimizations. Evolution of Kernels: Automated RISC-V Kernel Optimization with Large Language Models, which achieves a median 1.27x speedup in kernel design tasks.