The field of Electronic Design Automation (EDA) is witnessing a significant shift with the integration of Large Language Models (LLMs). Recent developments have demonstrated the potential of LLMs in simplifying and automating various aspects of the design-to-manufacturing workflow. Notably, LLMs are being leveraged to generate high-quality code, automate design tasks, and enhance verification and testing processes. The use of reinforcement learning and multi-agent architectures is also being explored to improve the performance and efficiency of LLMs in EDA. These advancements have the potential to significantly accelerate hardware development and reduce the complexity of modern integrated circuits. Noteworthy papers in this area include ASIC-Agent, which presents an autonomous multi-agent system for ASIC design, and VERIRL, which introduces a reinforcement learning framework for Verilog code generation. GENIE-ASI is also notable for its training-free, LLM-based methodology for analog subcircuit identification.