The field of computer architecture and formal verification is moving towards increased automation and pragmatism. Researchers are focusing on developing novel methodologies and tools to improve the efficiency and accuracy of formal verification, particularly in the context of emerging architectures such as RISC-V. Additionally, there is a growing emphasis on performance optimization, with a focus on developing practical and robust methods for extracting actionable insights from complex systems. Noteworthy papers include: On Automating Proofs of Multiplier Adder Trees using the RTL Books, which presents an experimental verified clause processor that automates the ACL2 proof development effort for integer multiplier modules. Dissecting RISC-V Performance: Practical PMU Profiling and Hardware-Agnostic Roofline Analysis on Emerging Platforms, which delivers a pragmatic methodology for extracting performance insights on RISC-V systems, even under constrained or unreliable hardware conditions.