The field of hardware design verification and code synthesis is witnessing a significant shift towards leveraging large language models (LLMs) and artificial intelligence (AI) to improve efficiency and accuracy. Researchers are exploring innovative approaches to integrate LLMs with domain-specific knowledge and expertise to automate tasks such as SystemVerilog Assertions (SVAs) generation and Standard Verification Rule Format (SVRF) code synthesis. These advancements have the potential to greatly reduce manual error correction, improve overall productivity, and enable rapid iteration through design cycles. Noteworthy papers in this area include: Hybrid-NL2SVA, which propose a customized retrieval-augmented generation framework and fine-tuning dataset to improve LLM performance in NL2SVA, resulting in a 58.42% increase in functionality matched SVAs. An AST-guided LLM Approach for SVRF Code Synthesis, which introduces a novel methodology integrating Abstract Syntax Tree (AST) embedding and Retrieval-Augmented Generation (RAG) for enhanced SVRF code synthesis, achieving up to a 40% improvement in code generation accuracy. Hey AI, Generate Me a Hardware Code, which presents an agentic AI-based approach to hardware design verification, demonstrating superior performance, adaptability, and configurability, and achieving over 95% coverage with reduced verification time.