The field of computer architecture is witnessing a significant shift towards in-memory computing and AI-optimized hardware designs. Recent developments focus on overcoming the traditional von Neumann bottlenecks by integrating computational capabilities within memory units, thereby reducing data movement overhead and enhancing overall performance and energy efficiency. Notable advancements include the use of photonic and non-volatile memory technologies to achieve ultra-fast and low-power computing. Additionally, researchers are exploring novel circuit designs and architectures that facilitate seamless integration of processing and memory units. Furthermore, there is a growing emphasis on developing domain-specific hardware and software solutions tailored to the needs of AI workloads, including optimized interconnect protocols and error correction mechanisms. While several papers contributed to the advancement of the field, a few stood out for their innovative approaches. The X-pSRAM proposal introduced a novel photonic SRAM design that enables ultra-fast in-memory Boolean computation. The CMOS+X integration of amorphous oxide semiconductor transistors in capacitive, persistent memory topologies offered a promising alternative to traditional SRAM designs.
Advancements in In-Memory Computing and AI-Optimized Hardware
Sources
X-pSRAM: A Photonic SRAM with Embedded XOR Logic for Ultra-Fast In-Memory Computing
SPI-BoTER: Error Compensation for Industrial Robots via Sparse Attention Masking and Hybrid Loss with Spatial-Physical Information
Stateful Logic In-Memory Using Gain-Cell eDRAM
CMOS+X: Stacking Persistent Embedded Memories based on Oxide Transistors upon GPGPU Platforms
Segmented Operations using Matrix Multiplications
Control-Optimized Deep Reinforcement Learning for Artificially Intelligent Autonomous Systems
Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems
Scaling Out Chip Interconnect Networks with Implicit Sequence Numbers
Deep Reinforcement Learning-Based DRAM Equalizer Parameter Optimization Using Latent Representations
Breaking the HBM Bit Cost Barrier: Domain-Specific ECC for AI Inference Infrastructure