The field of hardware design automation is experiencing significant advancements with the integration of large language models (LLMs). Researchers are exploring the potential of LLMs to improve the efficiency and accuracy of hardware design and verification processes. Notably, LLMs are being used to generate hardware code, automate reference model design and verification, and enhance the portability of existing code across different instruction set architectures. These innovations have the potential to revolutionize the field of hardware design automation, enabling faster and more reliable development of complex hardware systems. Some papers are particularly noteworthy for their innovative approaches and significant contributions to the field. For example, Spec2RTL-Agent has introduced a novel multi-agent collaboration framework for automated hardware code generation from complex specifications. Guaranteed Guess has proposed an ISA-centric transpilation pipeline that combines the translation power of pre-trained LLMs with the rigor of established software testing constructs. These advances demonstrate the exciting possibilities of LLMs in hardware design automation and are expected to have a significant impact on the field in the coming years.
Advances in Hardware Design Automation with Large Language Models
Sources
EmbedAgent: Benchmarking Large Language Models in Embedded System Development
Spec2RTL-Agent: Automated Hardware Code Generation from Complex Specifications Using LLM Agent Systems
SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine
Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification
Guaranteed Guess: A Language Modeling Approach for CISC-to-RISC Transpilation with Testing Guarantees
ChatModel: Automating Reference Model Design and Verification with LLMs