The field of FPGA and integrated circuit architecture is witnessing significant advancements, with a focus on improving performance, reducing power consumption, and increasing efficiency. Researchers are exploring innovative approaches to 3D FPGA architecture, cache efficiency, and data transmission in 3D-integrated circuits. Notable developments include the introduction of open-source frameworks for automated 3D FPGA architecture generation and evaluation, as well as architecture-scheduling co-designs to enhance cache efficiency for multi-tenant DNNs. Additionally, new encoding schemes and data movement optimization techniques are being proposed to reduce crosstalk and improve signal integrity in high-speed data transmission. Noteworthy papers include: LaZagna, which presents an open-source framework for flexible 3D FPGA architectural exploration, and CaMDN, which proposes an architecture-scheduling co-design to enhance cache efficiency for multi-tenant DNNs. Energy-Efficient Ternary Encoding is also noteworthy for its proposal of a ternary signalling scheme to reduce crosstalk and electromagnetic interference in multi-stacked chip communications.