The field of RISC-V architecture and cache coherence is moving towards increased programmability and performance. Researchers are exploring new designs and implementations that can improve the efficiency and flexibility of RISC-V based systems. One key area of focus is the development of programmable cache coherence engines, which can enable more efficient use of shared resources in multicore processors. Additionally, there is a growing interest in adapting RISC-V architectures for extreme edge applications, where power efficiency and flexibility are crucial. Noteworthy papers in this area include: The Open-Source BlackParrot-BedRock Cache Coherence System, which demonstrates the feasibility of including programmable logic within the coherence system of modern shared-memory multicore processors. CVA6S+: A Superscalar RISC-V Core with High-Throughput Memory Architecture, which introduces an enhanced RISC-V core with improved branch prediction and register renaming, resulting in significant performance improvements. Flexing RISC-V Instruction Subset Processors (RISPs) to Extreme Edge, which presents a methodology for automatically generating processors that support a subset of the RISC-V instruction set, achieving significant reductions in power and area compared to traditional RISC-V processors.