The field of compute-in-memory (CIM) architectures is rapidly advancing, with a focus on addressing the 'memory wall' bottleneck and improving the efficiency of deep neural network (DNN) acceleration. Recent developments have led to the creation of integrated frameworks that provide a comprehensive workflow for implementing and evaluating DNN workloads on digital CIM architectures. These frameworks enable systematic prototyping and optimization of digital CIM architectures, allowing researchers and designers to explore a wide range of design spaces. Additionally, novel compilation techniques have been proposed to explore a larger search space of programs, reducing memory requirements and improving throughput. The use of analog computing-in-memory (ACIM) is also being explored, with advances in modeling device- and circuit-level non-idealities and improved software backbones for benchmarking ACIM accelerators. Noteworthy papers include:

• CIMFlow, which provides an integrated framework for systematic design and evaluation of digital CIM architectures.
• Morello, which introduces a dynamic-programming-based approach to compile fast neural networks with improved throughput.
• NeuroSim V1.5, which advances the design and validation of next-generation ACIM accelerators with improved modeling of device- and circuit-level non-idealities.
• PUDTune, which presents a novel high-precision calibration technique for increasing the number of error-free columns in processing-using-DRAM.